1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and a method of manufacturing the same. The present invention especially relates to a nonvolatile semiconductor memory which can electrically erase/write data and to a method of manufacturing the same.
2. Description of Background Art
As a nonvolatile semiconductor memory which can electrically erase and write data, a flash memory and a charge trapping memory are known. The charge trapping memory stores data by using an element for trapping electric charge. The element for trapping electric charge is, for example, a MONOS (Metal oxide Nitride Oxide Silicon) transistor. The MONOS transistor is a sort of a MIS (Metal Insulator Semiconductor) transistor, and uses an ONO (Oxide Nitride Oxide) film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are laminated in order as a gate insulating film.
The silicon nitride film of the ONO film has a characteristic of trapping electric charge. For example, by applying appropriate voltages to a gate electrode, a source and drain, and a substrate, the silicon nitride film can trap electrons. When the electrons are trapped by the silicon nitride film, a threshold voltage of the MONOS transistor increases compared to a case that any electron is not trapped. To the contrary, when the trapped electrons are drawn from the silicon nitride film, the threshold voltage decreases. The MONOS transistor can store data of “1” and “0” in a nonvolatile manner by using a change of the threshold voltage. That is, the charge trapping memory stores data by using the MONOS transistor as a memory cell.
In recent years, a charge trapping memory can store 2-bit data in one memory cell has also been develop, as described in Japanese Patent Application Publication (JP-P2005-260164A).
FIG. 1 is a sectional view showing a charge trapping memory described in Japanese Patent Application Publication (JP-P2005-260164A). In FIG. 1, a memory cell 102 is formed on a silicon substrate 101. The memory cell 102 includes two MONOS transistors. In more detailed, source/drain diffusion layers 103 are formed in a surface of the silicon substrate 101. A first gate electrode 106 is formed via a gate insulating film 105 on a part of a channel region 104 between the source/drain diffusion layers 103. An ONO film 107 is formed in an L-shape on either end of a first gate electrode 106, and a second gate electrode 108 is formed on each of the ONO films 107. That is, the respective ONO films 107 are formed between the second gate electrode 108 and the channel region 104 and between the second gate electrode 108 and the first gate electrode 106. The ONO film 107 functions as an electric charge trapping layer for trapping electric charge. Thus, 2-bit data is stored in one memory cell 102.
Moreover, in FIG. 1, a first silicide layer 109 is formed on a center of an upper surface of the first gate electrode 106. In addition, a second silicide layer 110 is formed on the second gate electrode 108. As shown in FIG. 1, a height of a top of the second gate electrode 108 is higher than a height of a top of the first gate electrode 106. For this reason, a short-circuit between the first silicide layer 109 and the second silicide layer 110 is avoided in the formation of the silicide. That is, the resistance value of the second gate electrode 108 can be reduced while insulating the second gate electrode 108 from the first gate electrode 106.